The present invention relates to a CMOS SRAM cell and, more particularly, to a CMOS SRAM cell with prescribed power-on data state, i.e., a cell that assumes a known data state when powered-on.
FIG. 1 illustrates a standard CMOS static RAM cell defined by six MOS transistors T1, T2, T3, T4, T5, and TG; of these transistors, transistors T1 and T2 are PMOS transistors while the remaining transistors are of the NMOS type. Transistors T1 and T3 are serially connected between Vdd and ground to form a first inverter with a data node A between the two transistors, and, in a similar manner, transistors T2 and T4 are likewise connected between Vdd and ground to form a second inverter with a data node B therebetween. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. The transistor T5 is connected between the bit line BL and the data node A to provide data access thereto, and the transistor T6 is connected between the complementary bit line BLC and the data node B to similarly provide data access. The gates of the data access transistors T5 and T6 are connected to respective word lines WL; ancillary circuitry including differential-input sense amplifiers are not shown in FIG. 1.
The cross-coupled inverters of the memory cell of FIG. 1 have two stable states functioning to store either a binary one or a binary zero. More specifically, the data access transistors T5 and T6 are gated into conduction by an appropriate voltage applied to the respective word lines WL while a binary high is impressed on data node A via the bit line BL and a binary low is impressed on the complementary bit line BLC. The transistor T4 conducts to pull the data node B toward ground (binary low) while the data node A goes high. The opposite data state can be achieved by reversing the signals applied to the bit lines BL and BLC.
The representative memory cell of FIG. 1 is substantially bi-directionally symmetrical, this is, currents, voltage levels, and time durations are generally the same for either stable state. However, small differences between cells, such as manufacturing variations, doping variations, and other imbalances are such that the data state (i.e., a binary one or a binary zero) of a particular cell, upon power-up, cannot be predicted. Thus, in the context of a multi-cell memory array, the memory state of the multitude of cells cannot be known at power-up.
Known approaches to designing SRAM cells to have a known power-on data state have generally involved either asymmetrically designing the latch transistors of the cell so as to skew the switching thresholds of the cross-coupled inverters within the latch or by adding extra resistive and/or capacitive loading to one of the latch nodes to create asymmetric gate charging. These approaches undesirably causes the cell size to grow significantly, which is contrary to the objective of increasing the functional density of advanced microelectronics.
In view of the above, it is an object of the present invention, among others, to provide a CMOS SRAM cell with prescribed power-on data state.
It is another object of the present invention to provide a CMOS SRAM cell with prescribed power-on data state utilizing a PN junction in the gate circuit of one of the latches that define the cell.
It is still another object of the present invention to provide a CMOS SRAM cell with prescribed power-on data state an embedded PN junction in the gate circuit of one of the latches that define the cell.
In view of these objects, and others, the present invention provides a CMOS SRAM cell with prescribed power-on data state having first and second cross-coupled inverters each defined by serially connected complementary MOS transistors serially connected to form a first inverter with a first data node between the two transistors of the first inverter and a second inverter with a second data node between the two transistors of the second inverter. The gates of transistors of each inverter are connected together and cross-coupled to the data node of the other inverter. An access transistor is connected between a bit line and the first data node and another access transistor is connected between a complementary bit line and the second data node to provide data access thereto. A diode is connected in the gate circuit between the complementary P and N type MOS transistors of one of the two latches to change the gate charge time to assure that each latch will assume a pre-determined state upon power-up. The diode can be implemented in dual work function polysilicon topologies by selectively doping adjacent regions of the single gate-level polysilicon with an appropriate polysilicon doping type and concentration for each transistor type to form a PN junction in the polysilicon. A window or opening is formed in the silicide strapping layer to enable the PN junction operation.
The present invention advantageously provides a CMOS SRAM cell with prescribed power-on data state but utilizing a PN polysilicon junction layer without increasing feature size or cell size.
Other objects and further scope of applicability of the present invention will become apparent from the detailed description to follow, taken in conjunction with the accompanying drawings, in which like parts are designated by like reference characters.